Embodiments of the disclosed technology relate to a thin film transistor, an array substrate and a manufacturing method thereof.
At present, liquid crystal displays are commonly used flat panel displays, and thin film transistor liquid crystal displays (TFT-LCDs) are the mainstream products of the liquid crystal displays. In recent years, high aperture ratio fringe field switch (HFFS) type LCD is one of the focused development directions to achieve wide view angle display effect.
A liquid crystal panel of an HFFS type LCD is formed by bonding an array substrate and a color filter substrate. The array substrate comprises a base substrate on which a plurality of data lines and a plurality of gate lines intercrossing with each other are formed to define a plurality of pixel units arranged in matrix. Each of the pixel units comprises a TFT switch, a pixel electrode and a common electrode, and a fringe electrical field for driving the rotation of the liquid crystal is formed between the pixel electrode and the common electrode. The TFT switch comprises a gate electrode, a source electrode, a drain electrode and an active layer with the gate electrode connected with a corresponding gate line, the source electrode connected with a corresponding data line, the drain electrode connected with the pixel electrode, and the active layer being formed between the source/drain electrodes and the gate electrode. A typical laminate structure of the various conductive patterns on the HFFS type array substrate is as follows: a gate insulating layer is formed on the gate electrode and the gate line; the data line, the source electrode, the drain electrode, the active layer and the pixel electrode are formed on the gate insulating layer; a passivation layer is formed on the pixel electrode, and the common electrode is formed on the passivation layer.
The patterns of the data line, the source electrode and the drain electrode are generally formed by a single-mask patterning process with a double-tone mask when array substrates of other types (such as twisted nematic type, TN type) are fabricated. However, if the above patterning process is used in manufacturing the HFFS type array substrate, problems occur due to the following reasons. FIGS. 1A-1E show a specific procedure for manufacturing an HFFS type array substrate with a five-mask patterning process. At first, an active layer film 21 and a source/drain metal film 22 are deposited sequentially on a gate insulating layer 4, and the active layer film 21 generally comprises a semiconductor film 23 and a doped semiconductor film 24 from the bottom to the top. Thereafter, a photoresist layer 25 is applied, and then is exposed with a double-tone mask and developed to form a photoresist pattern with a photoresist-completely-remained region, a photoresist-partially-remained region and a photoresist-completely-removed region. A first etching is performed on a portion corresponding to the photoresist-completely-remained region. Specifically, the source/drain metal film 22 corresponding to the photoresist-completely-remained region is removed, as shown in FIG. 1A; and the semiconductor film 23 and the doped semiconductor film 24 corresponding to the photoresist-completely-remained region is removed, as shown in FIG. 1B; thus, a data line, a source electrode and a drain electrode are formed. The data line, the source electrode and the drain electrode are etched according to their respective desired line width. The photoresist layer 25 is then thinned by an amount corresponding to the thickness of the photoresist-partially-remained region, as shown in FIG. 1C, and the photoresist layer 25 in the photoresist-partially-remained region is removed completely. Then the source/drain metal film 22 corresponding to the photoresist-partially-remained region is etched by a dry etch method, as shown in FIG. 1D; and the doped semiconductor film 24 in the active layer film 21 is etched by a dry etch method so as to form the active layer with a defined channel, as shown in FIG. 1E. Finally, the remained portion of the photoresist layer 25 is removed so as to continue the subsequent processes. The above mentioned etching on the source electrode, the drain electrode and the active layer film may be controlled with the etching time to ensure the etching thickness of the films, so as to reach the predetermined etching positions consistent with the photoresist pattern.
In the above solutions, after the data line, the source electrode 7, and the drain electrode 8 are formed, as shown in FIG. 2, the slope angle of the edges of the source electrode 7 and the drain electrode 8 is relatively large; further, some residual doped semiconductor layer film 24 (n+ fence) exists at the periphery of the source electrode 7 and the drain electrode 8. Therefore, if a pixel electrode 11 is formed thereon later, as shown in FIG. 2, several corners are formed at the locations for lap-jointing between the pixel electrode 11 and the drain electrode 8. Furthermore, if the thicknesses of the source/drain metal film, the semiconductor film and the doped semiconductor film are larger than the thickness of the transparent conductive film used for the pixel electrode 11, cracks are likely to occur in the pixel electrode 11 at the corners, which can lead to defective displaying.
The above structural defect is not limited to the HFFS type array substrate, and the defects may also exist in the structure in which a relatively thin transparent electrode is directly lap-jointed on the drain electrode. In order to overcome the above defects, a conventional resolution is to form the pixel electrode between the active layer and the data line, the source electrode and the drain electrode. That is to say, the active layer, the pixel electrode, and the data line, the source electrode and the drain electrode are formed with three patterning processes, respectively, which obviously increases the times of the patterning processes. For example, the HFFS type array substrate is generally fabricated with a six-mask process (6Mask).